1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a configuration for reducing the current consumption in a standby state. The invention relates, more particularly, to a configuration for detecting, down to a minute current level, a leak current caused by a micro short circuit between a word line (row line) and a bit line, or the like, (column line) so as to repair this micro current path.
2. Description of the Background Art
FIG. 22 is a diagram schematically showing the configuration of an array part of a conventional semiconductor memory device. In FIG. 22, the configuration of a part related to bit lines of a dynamic random access memory (DRAM) requiring a refreshing operation that data is periodically restored.
In FIG. 22, memory cells MC are arranged in rows and columns. Corresponding to respective columns of the memory cells MC, bit line (column line) pairs BL0, /BL0 to BLn, /BLn are arranged. These bit line pairs BL0, /BL0 to BLn, /BLn are provided with bit line related circuits BK0 to BKn, respectively, and the configuration of the bit line related circuit BK0 corresponding to the bit line pair BL0 and /BL0 is specifically shown in FIG. 21.
The bit line related circuit BK0 includes a memory cell MCa provided corresponding to a crossing between the bit line BL0 and the word line WL0, a memory cell MCb arranged corresponding to a crossing between the bit line /BL0 and the word line WL1, a bit line isolation gate 3 responsive to a bit line isolation instructing signal BIL for isolating the bit lines BL0 and /BL0 from common bit lines CBL0 and /CBL0, a sense amplifier 2 responsive to activation of sense amplifier driving signals SP and SN,for amplifying the difference of voltages between the common bit lines CBL0 and /CBL0 and a bit line precharging/equalizing circuit 1 activated upon activation of a bit line precharging/equalizing instructing signal BLEQ for precharging and equalizing the bit lines BL0 and /BL0 to a predetermined precharge voltage PBL0 level via the common bit lines CBL0 and /CBL0.
The same configuration is provided in the remaining bit line related circuits BKm to BKn.
The memory cells arranged in alignment in one row are connected to each of the word lines WL0 and WL1.
The bit line isolation instructing signal BIL is applied in common to bit line isolation gates 3 included in these bit line related circuits BK0 to BKn. In the same manner, the sense amplifier driving signals SP and SN are applied in common to sense amplifiers 2 included in these bit line related circuits BK0 to BKn.
The bit line precharging/equalizing instructing signal BLEQ is applied in common to the bit line precharging/equalizing circuits 1 included in these bit line related circuits BK0 to BKn. The bit line precharging/equalizing circuits 1 are divided into a plurality of groups. In FIG. 22, the bit line precharging/equalizing circuits 1 included in the bit line related circuits BK0 to BKm, form one group and the bit line precharging/equalizing circuits 1 included in the bit line related circuits BKm+1 to BKn form another group.
The bit line precharging/equalizing circuits 1 included in the bit line related circuits BK0 to BKm are connected to a local intermediate voltage transmission line 6a, and the bit line precharging/equalizing circuits included in the bit line related circuits BKm+1 to BKn are connected to a local intermediate voltage transmission line 6b. The local intermediate voltage transmission lines 6a and 6b are linked to the main intermediate voltage transmission line 5 via fusible link elements (fuse elements) 4a and 4b, respectively.
The memory cells MCa and MCb each include a capacitor QS for storing information and an access transistor (N channel MOS transistor) MT responsive to a signal potential on the corresponding word line WL (WL0, WL1) for connecting the capacitor QS to the corresponding bit line BL (BL0, /BL0).
The bit line isolation gates 3 each include a pair of transfer gates responsive to the bit line isolation instructing signals BIL for connecting the bit lines BL0 and /BL0 to the common bit lines CBL0 and /CBL0, respectively. These bit line isolation gates 3 are provided because this DRAM has a shared sense amplifier configuration so that the sense amplifier 2 is shared between the adjacent bit line pairs, which are not shown. Upon reading out of data of the memory cells, the memory array, which includes a selected memory cell, is connected to the sense amplifiers 2, while the non-selected memory array (memory array where no selected memory cells is present) is isolated from the corresponding sense amplifiers 2 by means of the corresponding bit line isolation gate.
The sense amplifier 2 includes a P sense amplifier responsive to activation of the sense amplifier driving signal SP for driving a common bit line of higher potential out of the common bit lines CBL0 and /CBL0 to the H level (logical high level) and an N sense amplifier for driving a common bit line of lower potential out of the common bit lines CBL0 and /CBL0 to the L level upon activation of the sense amplifier driving signal SN.
The P sense amplifier includes P channel MOS transistors P1 and P2, having their gates and drains cross-coupled, while the N sense amplifier includes N channel MOS transistors N1 and N2 having their gates and drains cross-coupled. The sense amplifier driving signal SP is applied to the sources of these P channel MOS transistors P1 and P2, while the sense amplifier driving signal SN is applied to the sources of the N channel MOS transistors N1 and N2.
The bit line precharging/equalizing circuit 1 includes N channel MOS transistors N3 to N5 responsive to activation of the bit line precharging/equalizing signal BLEQ to become conductive. When rendered conductive, the N channel MOS transistor N3 electrically short circuits the common bit lines CBL0 and /CBL0. When rendered conductive, the N channel MOS transistors N4 and N5 transmit the intermediate voltage VBL, which is transmitted onto the local intermediate voltage transmission line 6a to the common bit lines CBL0 and /CBL0, respectively. This intermediate voltage VBL is normally a voltage level of xc2xd times the voltages corresponding to the H level and to the L level of the data stored in memory cells.
In the standby state, the bit line isolation instruction signal BIL is at the H level (normally a voltage level higher than the power supply voltage) and the bit line isolation gates 3 in the bit line related circuits BK0 to BKn are all in the conductive state. In the standby state, the bit line precharging/equalizing instruction signal BLEQ is also at the H level and the MOS transistors N3 to N5 in the bit line precharging/equalizing circuits 1 are all in the ON state, and the bit lines BL0, /BL0 to BLn /BLn are all precharged and equalized to the intermediate voltage VBL level. The word lines WL0 and WL1 are in the non-selected state at the L level, and the access transistors in the memory cells MCa and MCb are in the non-conductive state.
In the memory cell selection operation, first, the bit line precharging/equalizing instruction signal BLEQ becomes the L level, and in the bit line related circuits BK0 to BKn, the bit line precharging/equalizing circuits 1 transition into the non-activate state, and the bit lines BL0, /BL0 to BLn, /BLn transition into the floating state at this intermediate voltage VBL level.
Then, an addressed row is driven to the selected state and data of the memory cells connected to this selected word line are transmitted to the corresponding bit lines. In the case where the word line WL0 is selected, the voltage level of this word line WL0 attains the H level and the access transistor MT in the memory cell MCa transitions into the ON state so that the charge held by the memory cell capacitor QS is transmitted to the corresponding bit line BL0. The word line WL1 is in the non-selected state and no memory cell data are transmitted to the bit line /BL0, and the bit line /BL0 maintains the level of the intermediate voltage VBL.
In the selection of the word line WL0, the bit line isolation instruction signal BIL is at the H level and the bit line isolation gates 3 are in the ON state so that the bit lines BL0, /BL0 to BLn, /BLn are connected to the corresponding common bit lines CBL0, /CBL0 to CBLn, /CBLn, respectively. On the other hand, the bit line isolation gates provided for a not shown memory array (memory array which shares the sense amplifier 2) are turned into the OFF state so that this non-selected memory array is isolated from the sense amplifiers 2.
When the memory cell data is transmitted to the common bit lines CBL0, /CBL0 and the voltage difference becomes large, the sense amplifier driving signals SP and SN are driven to the H level and to the L level, respectively, at a predetermined timing, and the sense amplifier 2 carries out the sensing operation. Due to the sensing operation of this sense amplifier 2, the voltage levels of the common bit lines CBL0 and /CBL0 are set at the H level and the L level in accordance with the memory data of the memory cell MCa.
The voltages of these common bit lines CBL0, /CBL0 are also transmitted to the bit lines BL0, /BL0, and the rewriting (restoring) of the data to the memory cell MCa is performed.
Thereafter, a column selection operation is performed in accordance with a column selection instruction from an outside so that a not shown column selection gate provided corresponding to a selected column become conductive, and the writing in or the reading out of the data are performed for the selected memory cell on the selected column.
FIG. 23 is a diagram schematically showing the configuration of a bit line related circuit BK. Here, the case where a micro short circuit ZR exists between the word line WL and the bit line BL as shown in FIG. 23 is considered. The possibility of occurrence of such a micro short circuit ZR becomes higher when the miniaturization of the DRAM progresses to shorten the distance between the word line WL and the bit lines BL, /BL extremely because of the following reasons. Normally, the word line WL is connected to the gate of the access transistor MT, while the bit line BL is connected to the source/drain node of the access transistor MT. Along with the miniaturization of the access transistor, the distance between the word line and the bit lines BL, /BL becomes smaller so that short circuiting is more likely to occur because of the mixing in of contamination, or the like. In addition, because of the effect of a gap in an interlayer insulating film, a path for a short-circuit current tends to be easily formed between the word line and the bit line.
In the case where such a micro short circuit ZR occurs, a leak current constantly flows via this micro short circuit ZR.
In the standby state, the bit line precharging/equalizing circuit 1 is in the activate state, to transmit the intermediate voltage VBL to the bit lines BL and /BL. Now, the case is considered where a current supplied by the bit line precharging/equalizing circuit 1 is larger than the leak current I1s flowing through the micro short circuit ZR, and the voltage level of the bit lines BL and /BL is maintained at approximately the intermediate voltage VBL level in the standby state.
Now, the state as shown in FIG. 24 is considered where the word line WL is driven to the selected state when the L level data is maintained in the memory cell MC. The row selection operation is started in accordance with the array activation signal ACT. First, the bit line precharging/equalizing circuit 1 is deactivated and then, the word line WL is driven to the selected state. The L level data is transmitted to the bit line BL from the memory cell MC while the word line WL is driven to the H level and therefore, a leak current from the word line WL in the selected state flows to the bit line BL in the floating state, so that the voltage level of this bit line BL increases and the absolute value of the reading out voltage of the L level of the bit line BL becomes small. Accordingly, in the sensing operation, a sufficient voltage difference cannot be provided to the bit lines BL and /BL, which causes a sense margin defect, and therefore, a precise sensing operation cannot be performed.
In addition, in the case that the voltage level of the bit line BL rises to exceed the precharged voltage level due to the leak current from the selected word line via the micro short circuit in this short circuit state, the L level data may be sensed as the H level data depending on this voltage level, resulting in an incorrect sensing of the data.
Further, in the case, as shown in FIG. 25, that the word line WL is in the non-selected state and another word line WL is selected and the memory cell connected to the bit line BL stores the H level data, the H level data transmitted to this bit line BL are discharged via the micro short circuit ZR so that the voltage level of this bit line BL is lowered. In the same manner, a sensing margin defect occurs and therefore, a precise sensing operation cannot be performed. Such a defective bit line is replaced with a spare bit line pair, which is not shown, so that a repair of this defective bit line is performed.
However, since this defective bit line exists within the memory array, the leak current Ils flows constantly via this micro short circuit ZR in the standby state, to increase the standby current. In order to prevent the increase of standby current caused by such a leak current of the micro short circuit, the bit line pairs are divided into groups so that the link elements 4a and 4b are selectively blown off on a group unit. In the case that a defective bit line exists in each group, the corresponding link element 4 (4a or 4b) is blown off so that the local intermediate voltage transmission line 6 (6a or 6b) is isolated from the main intermediate voltage transmission line 5. Thereby, the current consumption in the standby state is reduced.
The case where a bit line defect is detected and the defect is repaired through a redundancy replacement by means of such link elements 4a and 4b, is limited to the case where the resistance value of the micro short circuit ZR is comparatively small. A function test is performed that the writing in/reading out of test data is performed for a memory cell, and a defect can be detected when the reading out of incorrect data occurs. The configuration intended to prevent the increase of the standby current due to such a defect of bit line short circuit is disclosed in, for example, U.S. Pat. No. 5,666,315.
As described above, it is necessary to carry out a function test of a memory cell so as to determine whether or not the writing in/reading out of data is performed precisely in order to detect a defect caused by such a micro short circuit ZR. Accordingly, in the case that the resistance value of this micro short circuit ZR is sufficiently large and the level of the current of the leak current Ils is so small as not to greatly influence the reading out voltage of bit lines, the defect cannot be detected during the function test and therefore, the micro short circuit (bit line short circuit) ZR of such a high resistance cannot be repaired.
In the case that such micro short circuits exist in a large number, the total standby leak current cannot be ignored.
In addition, in a battery driven application, such as in portable equipment, an extremely small standby current value is required, from the viewpoint of battery life, as a specification value of the standby current. Accordingly, the problem arises that, though normal operation is ensured even when a micro short circuit exists, the specification value of the ultra low standby current in the order of microampere (xcexcA) cannot be satisfied.
Such a problem is not limited to the micro short circuit between a bit line and a word line, and the same problem arises in the case that a micro short circuit exists between a bit line and a ground line.
An object of the present invention is to provide a semiconductor memory device allowing detection of a bit line leak current with a high precision so that a bit line defect is repaired.
Another object of the present invention is to provide a semiconductor memory device allowing the standby current to be greatly reduced.
A semiconductor memory device according to one aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of column lines arranged corresponding to respective columns, each connected to memory cells aligned on a corresponding column; a plurality of column line potential maintaining circuits provided corresponding to the plurality of column lines for maintaining the corresponding column lines at a predetermined potential when activated; a voltage transmission line for supplying the predetermined voltage to these column line potential maintaining circuits; a current control circuit for controlling a current flowing between the voltage transmission line and the column line maintaining circuits; and isolation circuits for isolating the corresponding column line potential maintaining circuits from said voltage transmission line. These isolation circuits are provided for every predetermined number of the column line potential maintaining circuits.
A semiconductor memory device according to another aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of column lines arranged corresponding to respective columns, each connected to memory cells aligned on a corresponding column; a plurality of row lines arranged corresponding to respective rows, each is connected to memory cells aligned on a corresponding row; a plurality of column line potential maintaining circuits which are coupled to the column lines, respectively, for maintaining corresponding column lines at a predetermined potential when made active; a row related circuit for deactivating the column line potential maintaining circuits and for driving a row line corresponding to an addressed row into a selected state in response to a memory cell selection instruction; and a test mode circuit for changing the time until the deactivation of the column line potential maintaining circuit and the row line selection by means of the row related circuit in response to a test mode instruction signal.
A semiconductor memory device according to a further aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of row lines arranged corresponding to respective rows, each connected to memory cells aligned on a corresponding row; a plurality of column lines arranged corresponding to respective columns, each connected to memory cells aligned on a corresponding column; column line potential maintaining circuits arranged corresponding to the plurality of these column lines for maintaining the corresponding column lines at a predetermined potential level when activated; a column line potential setting circuit for setting the holding potential of these column line potential maintaining circuits at a first potential level which is different from the predetermined potential in the test mode; a row line potential setting circuit for setting a predetermined number of row lines at a second potential which is different from said first potential in the test mode; and a circuit for reading out data of a selected memory cell.
By making the supply current of the column line potential maintenance circuit limitable, the potential of a column line can be changed by means of a leak current caused by a high resistance short circuit even when the high resistance short circuit, such as a micro short circuit, exists in the column line and thereby, a column line defect can be detected correctly. By isolating the column line potential maintenance circuit of the defective column line from the voltage transmission line, by means of an isolation circuit, a leak current in the standby state can be reduced.
In addition, by delaying the start of row line selection after transition into the memory cell selection cycle, the change of the potential of a column line can be made large by means of a leak current through the current leak path of this column line, and a column line defect can be detected correctly.
Further, by forcing a plurality of row lines into the selected state after once driving the column line into the first potential which is different from the potential of the selected row, in the case that a short circuit exists between a row line and a column line, the potential of this column line can be greatly changed so that the column line defect can be detected correctly.
In the detection of these column line defects, the current consumption in the standby state can be reduced by isolating a defective column from the voltage supply source.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.